Silicon-germanium epitaxial (Si—Ge epi) technology is becoming the mainstream in the application of heterojunction bipolar transistors. Si—Ge epi layers are used as the base material in such transistors in BiCMOS applications where bi-polar (BI) and complementary metal-oxide semiconductor (CMOS) transistors are fabricated in different areas of the same wafer. The Si—Ge epi layer could provide higher emitter injection efficiency and lower base transit time.
However, the discontinuity of the Si—Ge epi layer occurs on different intermediate layers and becomes a major issue for subsequent process steps due to poor polysilicon (poly) sheet resistance connected with the base electrode.
U.S. Pat. No. 6,388,307 B1 to Kondo et al. describes a B-doped SiGe layer in a transistor process.
U.S. Pat. No. 5,976,941 to Boles et al. describes a SiGe epi process.
U.S. Pat. No. 5,273,930 to Steele et al. describes a SiGe epi process on a silicon seed layer.
U.S. Pat. No. 5,620,907 to Jalali-Farahani et al. describes a method for a heterojunction bipolar transistor.